The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures including a vertical field-effect transistor, as well as methods of fabricating a structure including a vertical field-effect transistor.
Traditional complementary metal-oxide-semiconductor (CMOS) structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each other through the channel. Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate in conjunction with which they are formed. In a vertical field-effect transistor, the channel is located in a semiconductor fin that projects vertically from the surface of the semiconductor substrate and that is surrounded by a gate electrode. A source/drain region is arranged at the bottom of the semiconductor fin, and another source/drain region is arranged at the top of the semiconductor fin. The gate electrode is arranged vertically between the source/drain regions. The direction of the gated current flow in the channel between the source/drain regions is generally perpendicular (i.e., vertical) to the substrate surface and parallel to the height of the fin.
To be contacted from above with a middle-of-line contact, the bottom source/drain region protrudes laterally relative to the footprint of the gate electrode to provide an area for landing the middle-of-line contact that is vertically oriented. As a consequence of the enhanced area of the bottom source/drain region, the contact and series resistance of the bottom source/drain region may be higher than desirable. In addition, the requirement for a middle-of-line contact hinders the scaling of invertors formed using vertical field-effect transistors.
Improved structures including a vertical field-effect transistor and improved fabrication methods for a structure including a vertical field-effect transistor are needed.